FIG. 1 schematically shows an example of an embodiment of a phase-locked loop (PLL) 30. The PLL 30 may comprise, for example, a phase detector 32, a charge pump 34, a filter 36, an oscillator 38, and a frequency divider 40. In the shown example, the phase detector 32 is a phase-frequency detector (PFD). The oscillator 38 may be a voltage controlled oscillator (VCO) or any other kind of oscillator having a controllable frequency Fout (oscillator frequency). The frequency divider 40 may form part of a feedback loop arranged to ensure that the oscillator Fout becomes substantially identical to the frequency (reference frequency) Fref of a reference signal Sref and to lock the phase of the oscillator signal relative to the phase of the reference signal Sref.
The PFD 32 may have a first detector input 16 and a second detector input 17. The reference signal may be fed to the first detector input 16 as a first detector input signal S1. A feedback signal, with a frequency (feedback frequency) Ffb, may be generated by the frequency divider 40 in dependence of the oscillator signal and fed to the second detector input 17 as a second detector input signal S2. The reference signal and the feedback signal may be bi-level signals. A bi-level signal is a signal with only two allowed values, e.g., low and high or, equivalently, 0 and 1.
The PFD 32 may further have a first detector output 18 and a second detector output 19. The PFD 32 may be arranged to generate a phase difference signal (detector output signal) UP, DOWN in dependence of the reference signal and the feedback signal and to deliver the detector output signal via the first detector output 18 and the second detector output 19.
When the reference frequency Fref and the frequency Ffb are substantially equal, the detector output signal may be indicative of the phase difference between the feedback signal and the reference signal. The indicated phase difference may for example be restricted to the range of −π (or −180 degrees) and +π (or +180 degrees). The detector output signal may for instance be provided in terms of a first detector output signal (UP signal) and a second detector output signal (DOWN signal). The UP signal, provided for instance at the first detector output 18, and the DOWN signal, provided for instance at the second output 19, may be bi-level signals, for example.
When the phase difference is positive, its absolute value may for instance be represented by a duty cycle of the UP signal. A duty cycle may be defined as the duration of the HIGH phase of a periodic bi-level signal, that is the phase in which the signal is HIGH or at level “1” within a period. The duty cycle may be measured in periods of the signal and may then have a value in the range of 0 to 1. When the phase difference is positive, the duty cycle of the DOWN signal may be 0.
When the phase difference is negative, the duty cycle of the DOWN signal may indicate the absolute value of the phase difference between the reference signal and the feedback signal. The duty cycle of the UP signal may then be 0.
The phase difference Δφ may thus be expressed as Δφ=π*(DC_UP−DC_DOWN) wherein DC_UP and DC_DOWN are the duty cycles of the UP signal and the DOWN signal, respectively. Accordingly, the phase difference may be determined from the UP signal and the DOWN signal as Δφ=π*DC_UP when the phase difference is positive and Δφ=π*DC_DOWN when the phase difference is negative.
The detector output signal, i.e., a phase difference signal formed of the pair of signals UP and DOWN, may drive the charge pump 34 to translate the detector output signal into, e.g., a voltage corresponding to the phase difference. The thus generated voltage indicative of the phase difference may be fed to the voltage controlled oscillator 38. In the shown example, the voltage generated by the charge pump 34 may be fed to the VCO 38 via the filter 36. The filter 36 may be a low pass filter for filtering out possible high frequency components from the charge pump output signal. The filter 36 may thus contribute to the stability of the feedback loop. The controlled signal which is applied at the VCO 38 and which may be indicative of the phase difference between the feedback signal and the reference signal may be referred to as the VCO control signal. In the shown example, the VCO control signal may be generated from the phase detector output signal 18, 19 by means of the charge pump 34 and the filter 36. However, circuitry different from the units 34 and 36 shown here may be envisioned.
The VCO 38 may be arranged to adapt its oscillation frequency Fout in dependence of the VCO control signal. For instance, the VCO may decrease its oscillation frequency Fout in response to the VCO control signal indicating that the phase difference Δφ is positive. Similarly, the VCO 38 may increase its oscillation frequency Fout in response to the VCO control signal indicating that the phase difference is negative. The phase and frequency of the VCO output signal may thus be locked to the reference signal.
The scenario may be more complex when the frequency Ffb of the feedback signal and the frequency Fref of the reference signal differ. If, for example, the reference frequency is greater than the feedback frequency, the phase of the reference signal relative to a phase of the feedback signal will increase. When the phase difference indicated by the phase difference signal UP, DOWN is restricted to a range of, e.g., −π to or, e.g., 0 to 2*π, the indicated phase difference may increase in time continuously until it reaches the maximum phase difference value of, e.g., +π and then drop to its minimum allowed value of, e.g., −π. Generally, the phase difference indicated by the phase difference signal UP, DOWN produced by phase detector 32 may therefore be a discontinuous function of time.
FIG. 2 schematically illustrates an example of a phase detector 32 connected to a charge pump 34 (cf. “Trade-Offs in Analog Circuit Design: The Designer's Companion, Part II”, edited by Chris Toumazou, George S. Moschytz, and Barrie Gilbert, page 826, FIG. 28 6). The phase detector 32 may for example be the one shown in FIG. 1 as part of the PLL 30. The phase detector 32 may be arranged to measure a phase difference Δφ between a first bi-level signal (first detector input signal) S1 of frequency F1 and a second bi-level signal S2 (second detector input signal) S2 of frequency F2. The first bi-level signal S1 and the second bi-level signal S2 may be the reference signal Sref and the feedback signal Sfb. They may, for example, be provided in the form of voltages Vref and Vdiv. The phase detector 32 may comprise a first detector input 16 for receiving the first bi-level signal S1, a second detector input 17 for receiving the second bi-level signal S2, a first flip-flop 4, a second flip-flop 5, and a AND gate 7. The first detector input 16 may be connected to a clock input CLK of the first flip-flop 4. The second detector input 17 may be connected to a clock input CLK of the second flip-flop 5. A direct output UP of the first flip-flop 4 may be connected to a first input 20 of the AND gate 7. A direct output DN of the second flip-flop 5 may be connected to a second input 21 of the AND gate 7. An output of the AND gate 7 may be connected to an reset R of the first flip-flop 4 and to a reset input R of the second flip-flop 5.
A constant level of “1” or “high” may be applied at a direct input D of the first flip-flop 4 and at a direct input D of the second flip-flop 5. The direct output UP of the first flip-flop 4 and the direct output DN of the second flip-flop 5 may represent the first detector output 18 and the second detector output 19. The first detector output 18 and the second detector output 19 may be connected to a first switch and to a second switch, respectively, of the charge pump 34. The first switch of the charge pump 34 may be connected in series with a first current source P. The second switch of the charge pump 34 may be connected in series with a second current source N. The first switch may be arranged to be on, i.e. conductive, when the UP signal, i.e. the first detector output signal, is high and off, i.e. non conductive, when the UP signal is low. Similarly, the second switch may be arranged to be on when the second detector output signal is high and off when the second detector signal is low. An output node CPout of the charge pump 34 may thus provide a current ID which is a current pushed by the first current source P minus a current pulled by the second current source N. The current pushed by the first current source P when the first switch is closed (i.e. on or conductive) and the current pulled by the second current source N when the second switch is closed (i.e. on or conductive) may have the same amplitude. A time average of the output current ID may thus be proportional to the duty cycle of the UP signal minus the duty cycle of the DOWN signal. The time average of the output current ID may thus provide a measure of the phase difference between the first detector input signal Vref and the second detector input signal Vdiv.
More specifically, the phase detector 32 shown in FIG. 2 may operate as follows. If a rising edge of Vref is first, the first flip-flop 4 may be set to level 1. This state, i.e. the level 1, may be saved until the next rising edge of Vdiv which may set the second flip-flop 5 to level 1 for a brief moment. The AND gate 7 may then reset both flip-flops 4 and 5 to their initial states (level 0). The width of the UP signal may thus be proportional to the phase difference of the detector input signals Vref and Vdiv when the phase difference is positive.
Similarly, in another scenario the rising edge of Vdiv may be first and the second flip-flop may be set to level 1. The width of the signal DN may then be proportional to the negative phase difference of the detector input signals Vref and Vdiv.
The charge pump 34 may convert the widths of signals UP and DOWN with their signs to the output current ID. The filter 36 may convert this current to a voltage which may adjust the frequency of the voltage controlled oscillator 38.
This conventional phase detector may have linear phase characteristics for a phase difference from −2*π to +2*π, i.e. for equal frequencies of the input signals Vref and Vdiv, but exhibit sawtooth phase characteristics beyond this interval.